To reduce transistor size when SRAM cells or other types of cells are created using conventional planar transistors (see FIGS. 1A through 1C, in which 101 and 103 represent the source and drain, and 105 represents the gate), integrated circuit (IC) manufacturers generally adjust properties by doping more impurities into the device area. However this adjustment creates undesirable variability and deteriorates the circuit stability. This issue is critical at the 22 nm technology node and beyond. The use of finfets (see FIGS. 2A through 2C, in which 201 and 203 represent the source and drain, 205 represents the gate, and 207 represents the fin), vertical transistors with fin-shaped undoped silicon channels, has been proposed as an alternative approach to allow circuit size reduction with less characteristic variation.
To form fins on a substrate, a self-aligned double patterning (SADP) process is employed. For example, a coherent light source 301 is directed through a classical photomask 303 at a resist 305, as illustrated in FIG. 3A, and the resist is etched to form mandrels 307 (FIG. 3B). As shown in FIG. 3C, sidewall spacers 309 are then deposited on the sides of the mandrels 307 with conventional chemical and chemical mechanical polishing (CMP) processes. Finally, the mandrels are removed, for example by etching, leaving the fins on the substrate, as illustrated in FIG. 3D. The fins are placed over large areas, tightly spaced (e.g., having a space of 22 nm between adjacent fins and having a center-to-center pitch of 44 nm) and repetitively formed where transistors are to be fabricated. Once the fins are patterned, gates can be formed over the fin, as illustrated in FIG. 2C.
Adverting to FIGS. 4A and 4B, the gates 401 and either mandrels 403 or fins 405 form a regular layout with fixed spacings. Therefore, either the mandrels can be drawn or the fins can be drawn for the computer-aided design (CAD) layout, and then the actual mask can be generated from either pattern. For logic structures, the layout for mandrels is an ultra regular design, with ultra regular pitches, as illustrated in FIG. 5A. For SRAMs, however, the pitch varies, as shown in FIG. 5B. As illustrated in FIG. 5C, a chip may have ultra regular pattern 501 for the logic portion, which may cover more than 95% of the chip, and varying pitches at 503 for the SRAM portion.
When a pattern is printed on a wafer, the diffraction of light through the mask leads to distorted images on the wafer, for example images with corner rounding, line shortening, or even elimination of image portions. To end with the correct design on the wafer, a resist model or design model is prepared, incorporated into model software, and OPC is employed. OPC may be either rule based or model based. For full model based OPC, a calculation of how the image will look must be performed for every line, which is very time consuming. For a regular pattern, rule based OPC may be employed; once it is known how one portion will behave, the rules for correcting that portion can be applied for each repeat of that portion. Since the finfet mandrel layer for a full chip generally includes both regular and irregular patterns (for example, logic portions and SRAM portions), model based OPC is required.
A need therefore exists for methodology enabling faster OPC for finfet mandrel layers for full chip layouts including irregular patterns.